Non-volatile memories are a class of integrated circuits in which the memory cell or element does not lose its state after the power supplied to the device is turned off. The earliest computer memories, made with rings of ferrite that could be magnetized in two directions, were non-volatile. As semiconductor technology evolved into higher levels of miniaturization, the ferrite devices were abandoned for the more commonly known volatile memories, such as DRAMs (Dynamic Random Access Memories) and SRAMs (Static-RAMs).
The need for non-volatile memories never went away. Thus, in the last forty years, many devices were created to fulfill this need. In the late 70's, devices were made with a metallization layer which either connected or disconnected a cell. Thus, at the factory one could set values in a non-volatile way. Once these devices left the factory, they could not be re-written. They were called ROMs (Read Only Memories). In 1967, Khang and SZE at Bell Laboratories proposed devices which were made using field effect transistors (FETs) which had within layers of materials in the gate, the ability to trap charge. In the late 70's and early 80's, devices which could be written by the user and erased by de-trapping the electrons via ultra-violet light (UV) were very successful. The UV both required the device to be removed from the circuit board and placed under a UV lamp for over 15 minutes. These non-volatile memories were called PROMs or programmable ROMs. The writing process involved forcing current from the substrate below to these trap sites. This process of making the electrons pass through layers of materials which have an opposing potential energy barrier is known as quantum tunneling, a phenomenon that only occurs because of the wave-particle duality of the electron. Many types of sandwiches of materials for the gate stack of these FETs were tried, and the technology received many names such as MNOS (Metal-Nitride-Oxide-Semiconductor), SNOS ([Poly] Silicon-Gate Plus MNOS), SONOS (Silicon-Oxide Plus MNOS) and PS/O/PS/S (Polysilicon Control Gate—Silicon Dioxide—Polysilicon Floating Gate—and a thin tunneling oxide on top of the silicon substrate). This kind of erasable, and thus, read/write non-volatile device was known as EEPROMs for electrically-erasable-PROMs, an unfortunate misnomer since they are not just read only. Typically, EEPROMS have large cell areas and require a large voltage (from 12 to 21 volts) on the gate in order to write/erase. Also, the erase or write time is of the order of tens of microseconds. However, the worse limiting factor is the limited number of erase/write cycles to no more than slightly over 600,000—or of the order of 105-106. The semiconductor industry eliminated the need of a pass-gate switch transistor between EEPROMs and non-volatile transistors by sectorizing the memory array in such a way that “pages” (sub-arrays) could be erased at a time in memories called Flash memories. In Flash memories, the ability to keep random access (erase/write single bits) was sacrificed for speed and higher bit density.
The desire to have low power, high speed, high density, and indestructibility has kept researchers working in non-volatile memory for the last forty years. FeRAMs (Ferroelectric RAMs) provide low power, high write/read speed, and endurance for read/write cycles exceeding 10 billion times. Magnetic memories (MRAMs) provide high write/read speed and endurance, but with a high cost premium and higher power consumption. Neither of these technologies reaches the density of Flash; thus, Flash remains the non-volatile memory of choice. However, it is generally recognized that Flash will not scale easily below 65 nanometers (nm); thus, new non-volatile memories that will scale to smaller sizes are actively being sought.
To this end, there has been much research over the last ten to twenty years on memories based on certain materials that exhibit a resistance change associated with a change of phase of the material. In one type of variable resistance memory called a PCM phase change memory), a change in resistance occurs when the memory element is melted briefly and then cooled to either a conductive crystalline state or a non-conductive amorphous state. Typical materials vary and include GeSbTe, where Sb and Te can be exchanged with other elements of the same properties on the Periodic Table. These materials are often referred to as chalcogenides. See, for example, Stephan Lai, “Current Status of the Phase Change Memory and Its Future”, Intel Corporation, Research note RN2-05 (2005); U.S. Pat. No. 7,038,935 issued to Darrell Rinerson et al., May 2, 2006; U.S. Pat. No. 6,903,361 issued to Terry L. Gilton on Jun. 7, 2005; and U.S. Pat. No. 6,841,833 issued to Sheng Teng Hsu et al., Jan. 11, 2005. However, these resistance-based memories have not proved to be commercially useful because their transition from the conductive to the insulating state depends on a physical structure phenomenon, i.e., melting (at up to 600° C.) and returning to a solid state that cannot be sufficiently controlled for a useful memory.
Recently, a resistance switching field effect transistor has been disclosed using a Mott-Brinkman-Rice insulator, such as LaTiO3. In this material, according to the theory proposed, the addition of holes via an interface with a Ba(1-X)SrXTiO3 layer changes the material from an insulator to a conductor. See U.S. Pat. No. 6,624,463 issued to Hyun-Tak Kim et al. on Sep. 23, 2003. This FET uses the Mott-Brinkman-Rice insulator as the channel in the FET. However, no example of fabrication of actual devices is given.
Another variable resistance memory category includes materials that require an initial high “forming” voltage and current to activate the variable resistance function. These materials include PrxCayMnzOε, with x, y, z and ε of varying stoichiometry; transition metal oxides, such as CuO, CoO, VOx, NiO, TiO2, Ta2O5; and some perovskites, such as Cr; SrTiO3. See, for example, “Resistive Switching Mechanisms of TiO2 Thin Films Grown By Atomic-Layer Deposition”, B. J. Choi et al., Journal of Applied Physics 98, 033715 (2005); “Reproducible Resistive Switching In Nonstoichiometric Nickel Oxide Films Grown By RF Reactive Sputtering For Resistive Random Access Memory Applications”, Jae-Wan Park, et al., J. Vac. Sci. Technol. A 23(5), September/October 2005; “Influence Of Oxygen Content On Electrical Properties Of NiO films grown By RF Reactive Sputtering”, Jae-Wan Park, et al., J. Vac. Sci. Technol. B 24(5), September/October 2006; “Nonpolar Resistance Switching Of Metal/Binary-Transition-Metal Oxides/Metal Sandwiches: Homogeneous/inhomogeneous Transition of Current Distribution”, I. H. Inone et al., arXiv:Condmat/0702564 v.1, 26 Feb. 2007; and U.S. Patent Application Publication No. 2007/0114509 A1, Memory Cell Comprising Nickel-Cobalt Oxide Switching Element, on an application of S. Brad Herner. These memories are referred to as ReRAMs, to distinguish them from the chalcogenide type memories. These papers postulate that the resistance switching is due to the formation of narrow conducting paths or filaments connecting the top and bottom electrodes by the electroforming process, though the presence of such conducting filaments are still a matter of controversy. It is believed by Applicants that, when electroforming is used, the bulk of the non-filament region does not provide true memory switching but a metastable electron storage which is due to charge trapping and detrapping in oxygen vacancies. FIG. 19 is an Arrhenius curve of the log of 1/Tau versus 1/T(1/K) for prior art sputtered NiO illustrating the transition from the high resistance state to the low resistance state in this typical prior art resistive switching material is caused by detrapping of electrons from oxygen vacancies in the sputtered NiO. To generate this Arrhenius curve, the relaxation time for the material to return to the insulative state after SET, Tau, was measured for a number of temperatures in the working range of a proposed variable resistance memory (below 70° C.) for NiO films made by sputtering. As is known in the art, the slope of the Arrhenius curve 30 is proportional to the activation energy for the mechanism that is causing the relaxation. The slope found from curve 30 yields an activation energy of approximately 0.47 eV. This is essentially the activation energy for detrapping of electrons from oxygen vacancies in NiO. See “Surface Metallic Nature Caused By An In-Gap State Of Reduced NiO: A Photoemission Study”, N. Nakajima et al., Journal of Electron Spectroscopy and Related Phenomena, 144 147 (2005) pp. 873-875. Thus, the variable resistance phenomenon of the prior art NiO devices is dominated by the trapping and detrapping of electrons in oxygen vacancies. Since trapping is strongly temperature dependent, such a resistive switching mechanism must also be highly temperature dependent; therefore, it cannot form the basis for a commercially useful memory. Similarly, all other prior art resistive switching materials exhibit unstable qualities. Further, the resistance switching tends to fatigue over many memory cycles. That is, after the memory state is changed many times, the resistance difference between the conducting and insulative states changes significantly. In a commercial memory, such a change would take the memory out of specification and make it unusable. Moreover, based on the ReRAM art to date, the use of such materials must be said to be speculative, since the high voltage-high current electroforming step simply is not compatible with dense chip architecture. In fact, the Herner patent application reference merely speculates that a combination of nickel and cobalt oxides will eliminate the required high amplitude pulses, without providing an actual example to demonstrate it.
In summary, there have been literally hundreds, if not thousands, of papers and patent applications written on resistive memories in the last ten years, most of which have been speculative. However, a workable resistance switching memory has never been made, because no one knows how to make a thin film resistance switching material that is stable over time and temperature. Further, all resistance switching mechanisms developed up to now have been inherently unsuitable for memories, due to high currents, electroforming, no measurable memory windows over a reasonable range of temperatures and voltages, and many other problems. Thus, there remains a need in the art for a non-volatile memory that has low power, high speed, high density and stability, and in particular, such a memory that is scalable to feature sizes well below 65 nanometers (nm).